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STM32标准库工程修改为GD32工程主频提高到108MHZ

   日期：2021-03-05     浏览：111    评论：0    
核心提示：一、准备工作移植前首先要有一个STM32F103的工程文件二、修改擦写时间将宏定义：#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500)修改为：#define HSE_STARTUP_TIMEOUT ((uint16_t)0xFFFF)三、修改时钟为108Mhz1、在"system_stm32f10x.c"中添加 #define SYSCLK_HSI_108MHz 108000000#if defined (STM32F10X_LD_VL) ||

一、准备工作
移植前首先要有一个STM32F103的工程文件
二、修改启动时间

将宏定义：
#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500)
修改为：
#define HSE_STARTUP_TIMEOUT ((uint16_t)0xFFFF)

三、修改时钟为108Mhz
1、在"system_stm32f10x.c"中添加 #define SYSCLK_HSI_108MHz 108000000

#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)

 #define SYSCLK_FREQ_24MHz 24000000
#else

 



//#define SYSCLK_FREQ_72MHz 72000000
#define SYSCLK_FREQ_108MHz 108000000
#endif

2、Clock Definitions继续添加


#ifdef SYSCLK_FREQ_HSE
  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        
#elif defined SYSCLK_FREQ_24MHz
  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        
#elif defined SYSCLK_FREQ_36MHz
  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        
#elif defined SYSCLK_FREQ_48MHz
  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        
#elif defined SYSCLK_FREQ_56MHz
  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        
#elif defined SYSCLK_FREQ_72MHz
  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        
#elif defined SYSCLK_FREQ_108MHz
  uint32_t SystemCoreClock         = SYSCLK_FREQ_108MHz;          
#else 
  uint32_t SystemCoreClock         = HSI_VALUE;        
#endif

3、添加设置时钟为108Mhz函数声明

#ifdef SYSCLK_FREQ_HSE
  static void SetSysClockToHSE(void);
#elif defined SYSCLK_FREQ_24MHz
  static void SetSysClockTo24(void);
#elif defined SYSCLK_FREQ_36MHz
  static void SetSysClockTo36(void);
#elif defined SYSCLK_FREQ_48MHz
  static void SetSysClockTo48(void);
#elif defined SYSCLK_FREQ_56MHz
  static void SetSysClockTo56(void);  
#elif defined SYSCLK_FREQ_72MHz
  static void SetSysClockTo72(void);
#elif defined SYSCLK_FREQ_108MHz
  static void SetSysClockTo108(void);  
#endif

4、添加void SetSysClockHSITo108(void)的函数

#elif defined SYSCLK_FREQ_108MHz

#define RCC_CFGR_PLLMULL27 ((uint32_t)0x08280000)
static void SetSysClockTo108(void)
{ 
	
	FLASH->ACR |= FLASH_ACR_PRFTBE;

	
	FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
	FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;

	
	RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

	
	RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;

	
	RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;

	
	RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
	RCC_CFGR_PLLMULL));
	RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLMULL27);

	
	RCC->CR |= RCC_CR_PLLON;

	
	while((RCC->CR & RCC_CR_PLLRDY) == 0)
	{ 
	}

	
	RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
	RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

	
	while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
	{ 
	}

}
#endif

至此时钟基本就修改完毕了。
四、修改RCC文件
时钟改为108Mhz后如果不修改RCC文件会导致串口不合适，时钟倍频到108MHz需要修改的就是system_stm32f10x.c文件,解决串口波特率问题需要修改的就是stm32f10x_rcc.c文件。具体不懂可以参考GD的手册。
修改后的 stm32f10x_rcc.c




#include "stm32f10x_rcc.h"



 








#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)




#define CR_OFFSET (RCC_OFFSET + 0x00)
#define HSION_BitNumber 0x00
#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))


#define PLLON_BitNumber 0x18
#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))

#ifdef STM32F10X_CL
 
 #define PLL2ON_BitNumber 0x1A
 #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))

 
 #define PLL3ON_BitNumber 0x1C
 #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))
#endif  


#define CSSON_BitNumber 0x13
#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))




#define CFGR_OFFSET (RCC_OFFSET + 0x04)

#ifndef STM32F10X_CL
 #define USBPRE_BitNumber 0x16
 #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
#else
 #define OTGFSPRE_BitNumber 0x16
 #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))
#endif  




#define BDCR_OFFSET (RCC_OFFSET + 0x20)
#define RTCEN_BitNumber 0x0F
#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))


#define BDRST_BitNumber 0x10
#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))




#define CSR_OFFSET (RCC_OFFSET + 0x24)
#define LSION_BitNumber 0x00
#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))

#ifdef STM32F10X_CL


 
 #define CFGR2_OFFSET (RCC_OFFSET + 0x2C)
 #define I2S2SRC_BitNumber 0x11
 #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))

 
 #define I2S3SRC_BitNumber 0x12
 #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))
#endif 




#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
#define CR_HSEBYP_Set ((uint32_t)0x00040000)
#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
#define CR_HSEON_Set ((uint32_t)0x00010000)
#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)


#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) 
 #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF)
#else
 #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)
#endif  

#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)
#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000)
#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)
#define CFGR_SWS_Mask ((uint32_t)0x0000000C)
#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)
#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)
#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)
#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)
#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)
#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)


#define CSR_RMVF_Set ((uint32_t)0x01000000)

#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) 

 #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000)
 #define CFGR2_PREDIV1 ((uint32_t)0x0000000F)
#endif
#ifdef STM32F10X_CL
 #define CFGR2_PREDIV2 ((uint32_t)0x000000F0)
 #define CFGR2_PLL2MUL ((uint32_t)0x00000F00)
 #define CFGR2_PLL3MUL ((uint32_t)0x0000F000)
#endif  


#define FLAG_Mask ((uint8_t)0x1F)


#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)


#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)


#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)


#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)

 

 

 

 

static __I uint8_t APBAHBPrescTable[16] = { 0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
static __I uint8_t ADCPrescTable[4] = { 2, 4, 6, 8};










void RCC_DeInit(void)
{ 
  
  RCC->CR |= (uint32_t)0x00000001;

  
#ifndef STM32F10X_CL
  RCC->CFGR &= (uint32_t)0xF8FF0000;
#else
  RCC->CFGR &= (uint32_t)0xF0FF0000;
#endif    
  
  
  RCC->CR &= (uint32_t)0xFEF6FFFF;

  
  RCC->CR &= (uint32_t)0xFFFBFFFF;

  
  RCC->CFGR &= (uint32_t)0xFF80FFFF;

#ifdef STM32F10X_CL
  
  RCC->CR &= (uint32_t)0xEBFFFFFF;

  
  RCC->CIR = 0x00FF0000;

  
  RCC->CFGR2 = 0x00000000;
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
  
  RCC->CIR = 0x009F0000;

  
  RCC->CFGR2 = 0x00000000;      
#else
  
  RCC->CIR = 0x009F0000;
#endif 

}


void RCC_HSEConfig(uint32_t RCC_HSE)
{ 
  
  assert_param(IS_RCC_HSE(RCC_HSE));
  
  
  RCC->CR &= CR_HSEON_Reset;
  
  RCC->CR &= CR_HSEBYP_Reset;
  
  switch(RCC_HSE)
  { 
    case RCC_HSE_ON:
      
      RCC->CR |= CR_HSEON_Set;
      break;
      
    case RCC_HSE_Bypass:
      
      RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
      break;
      
    default:
      break;
  }
}


ErrorStatus RCC_WaitForHSEStartUp(void)
{ 
  __IO uint32_t StartUpCounter = 0;
  ErrorStatus status = ERROR;
  FlagStatus HSEStatus = RESET;
  
  
  do
  { 
    HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
    StartUpCounter++;  
  } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
  
  if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
  { 
    status = SUCCESS;
  }
  else
  { 
    status = ERROR;
  }  
  return (status);
}


void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
{ 
  uint32_t tmpreg = 0;
  
  assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
  tmpreg = RCC->CR;
  
  tmpreg &= CR_HSITRIM_Mask;
  
  tmpreg |= (uint32_t)HSICalibrationValue << 3;
  
  RCC->CR = tmpreg;
}


void RCC_HSICmd(FunctionalState NewState)
{ 
  
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
}


void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
{ 
  uint32_t tmpreg = 0;

  
  assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
  assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));

  tmpreg = RCC->CFGR;
  
  tmpreg &= CFGR_PLL_Mask;
  
  tmpreg |= RCC_PLLSource | RCC_PLLMul;
  
  RCC->CFGR = tmpreg;
}


void RCC_PLLCmd(FunctionalState NewState)
{ 
  
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
}

#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)

void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
{ 
  uint32_t tmpreg = 0;
  
  
  assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));
  assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));

  tmpreg = RCC->CFGR2;
  
  tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);
  
  tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;
  
  RCC->CFGR2 = tmpreg;
}
#endif

#ifdef STM32F10X_CL

void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
{ 
  uint32_t tmpreg = 0;

  
  assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));

  tmpreg = RCC->CFGR2;
  
  tmpreg &= ~CFGR2_PREDIV2;
  
  tmpreg |= RCC_PREDIV2_Div;
  
  RCC->CFGR2 = tmpreg;
}


void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
{ 
  uint32_t tmpreg = 0;

  
  assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));

  tmpreg = RCC->CFGR2;
  
  tmpreg &= ~CFGR2_PLL2MUL;
  
  tmpreg |= RCC_PLL2Mul;
  
  RCC->CFGR2 = tmpreg;
}



void RCC_PLL2Cmd(FunctionalState NewState)
{ 
  
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;
}



void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
{ 
  uint32_t tmpreg = 0;

  
  assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));

  tmpreg = RCC->CFGR2;
  
  tmpreg &= ~CFGR2_PLL3MUL;
  
  tmpreg |= RCC_PLL3Mul;
  
  RCC->CFGR2 = tmpreg;
}



void RCC_PLL3Cmd(FunctionalState NewState)
{ 
  

  assert_param(IS_FUNCTIONAL_STATE(NewState));
  *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;
}
#endif 


void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
{ 
  uint32_t tmpreg = 0;
  
  assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
  tmpreg = RCC->CFGR;
  
  tmpreg &= CFGR_SW_Mask;
  
  tmpreg |= RCC_SYSCLKSource;
  
  RCC->CFGR = tmpreg;
}


uint8_t RCC_GetSYSCLKSource(void)
{ 
  return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
}


void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
{ 
  uint32_t tmpreg = 0;
  
  assert_param(IS_RCC_HCLK(RCC_SYSCLK));
  tmpreg = RCC->CFGR;
  
  tmpreg &= CFGR_HPRE_Reset_Mask;
  
  tmpreg |= RCC_SYSCLK;
  
  RCC->CFGR = tmpreg;
}


void RCC_PCLK1Config(uint32_t RCC_HCLK)
{ 
  uint32_t tmpreg = 0;
  
  assert_param(IS_RCC_PCLK(RCC_HCLK));
  tmpreg = RCC->CFGR;
  
  tmpreg &= CFGR_PPRE1_Reset_Mask;
  
  tmpreg |= RCC_HCLK;
  
  RCC->CFGR = tmpreg;
}


void RCC_PCLK2Config(uint32_t RCC_HCLK)
{ 
  uint32_t tmpreg = 0;
  
  assert_param(IS_RCC_PCLK(RCC_HCLK));
  tmpreg = RCC->CFGR;
  
  tmpreg &= CFGR_PPRE2_Reset_Mask;
  
  tmpreg |= RCC_HCLK << 3;
  
  RCC->CFGR = tmpreg;
}


void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
{ 
  
  assert_param(IS_RCC_IT(RCC_IT));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  if (NewState != DISABLE)
  { 
    
    *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
  }
  else
  { 
    
    *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
  }
}

#ifndef STM32F10X_CL

void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
{ 
  
  assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));

  *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
}
#else

void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
{ 
  
  assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));

  *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;
}
#endif  


void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
{ 
  uint32_t tmpreg = 0;
  
  assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
  tmpreg = RCC->CFGR;
  
  tmpreg &= CFGR_ADCPRE_Reset_Mask;
  
  tmpreg |= RCC_PCLK2;
  
  RCC->CFGR = tmpreg;
}

#ifdef STM32F10X_CL

void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
{ 
  
  assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));

  *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;
}


void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
{ 
  
  assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));

  *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;
}
#endif 


void RCC_LSEConfig(uint8_t RCC_LSE)
{ 
  
  assert_param(IS_RCC_LSE(RCC_LSE));
  
  
  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
  
  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
  
  switch(RCC_LSE)
  { 
    case RCC_LSE_ON:
      
      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
      break;
      
    case RCC_LSE_Bypass:
      
      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
      break;            
      
    default:
      break;      
  }
}


void RCC_LSICmd(FunctionalState NewState)
{ 
  
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
}


void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
{ 
  
  assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
  
  RCC->BDCR |= RCC_RTCCLKSource;
}


void RCC_RTCCLKCmd(FunctionalState NewState)
{ 
  
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
}


void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
{ 
  uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;

  
  tmp = RCC->CFGR & CFGR_SWS_Mask;
 
  switch (tmp)
  { 
    case 0x00:  
      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
      break;
    case 0x04:  
      RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
      break;
    case 0x08:  

      
      pllmull = RCC->CFGR &((uint32_t)0x083C0000);
      pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
      
    if(((pllmull)&(0x08000000)) != 0)
          pllmull = (((pllmull)&(0x003C0000)) >> 18) + 17;
      else
          pllmull = ( pllmull >> 18) +2;
      
      if (pllsource == 0x00)
      { 
        RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
      }
      else
      { 
        
        if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
        { 
          RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
        }
        else
        { 
          RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
        }
      }
      break;
    default:
      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
      break;
  }

  
  
  tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
  tmp = tmp >> 4;
  presc = APBAHBPrescTable[tmp];
  
  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
  
  tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
  tmp = tmp >> 8;
  presc = APBAHBPrescTable[tmp];
  
  RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
  
  tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
  tmp = tmp >> 11;
  presc = APBAHBPrescTable[tmp];
  
  RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
  
  tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
 tmp = (tmp >> 14)+(tmp >> 26);
  presc = ADCPrescTable[tmp];
  
  RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
}
//void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
//{ 
// uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;

//#ifdef STM32F10X_CL
// uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
//#endif 

//#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
// uint32_t prediv1factor = 0;
//#endif
// 
// 
// tmp = RCC->CFGR & CFGR_SWS_Mask;
// 
// switch (tmp)
// { 
// case 0x00: 
// RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
// break;
// case 0x04: 
// RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
// break;
// case 0x08: 

// 
// pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
// pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
// 
//#ifndef STM32F10X_CL 
// pllmull = ( pllmull >> 18) + 2;
// 
// if (pllsource == 0x00)
// {
// RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
// }
// else
// { 
// #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
// prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
// 
// RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; 
// #else
// 
// if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
// {
// RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
// }
// else
// { 
// RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
// }
// #endif
// }
//#else
// pllmull = pllmull >> 18;
// 
// if (pllmull != 0x0D)
// { 
// pllmull += 2;
// }
// else
// { 
// pllmull = 13 / 2; 
// }
// 
// if (pllsource == 0x00)
// {
// RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
// }
// else
// {
// 
// 
// prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
// prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
// 
// if (prediv1source == 0)
// { 
// RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; 
// }
// else
// {
// 
// 
// prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
// pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; 
// RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; 
// }
// }
//#endif  
// break;

// default:
// RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
// break;
// }

// 
// 
// tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
// tmp = tmp >> 4;
// presc = APBAHBPrescTable[tmp];
// 
// RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
// 
// tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
// tmp = tmp >> 8;
// presc = APBAHBPrescTable[tmp];
// 
// RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
// 
// tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
// tmp = tmp >> 11;
// presc = APBAHBPrescTable[tmp];
// 
// RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
// 
// tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
// tmp = tmp >> 14;
// presc = ADCPrescTable[tmp];
// 
// RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
//}

void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
{ 
  
  assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
  { 
    RCC->AHBENR |= RCC_AHBPeriph;
  }
  else
  { 
    RCC->AHBENR &= ~RCC_AHBPeriph;
  }
}


void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
{ 
  
  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  if (NewState != DISABLE)
  { 
    RCC->APB2ENR |= RCC_APB2Periph;
  }
  else
  { 
    RCC->APB2ENR &= ~RCC_APB2Periph;
  }
}


void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
{ 
  
  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  if (NewState != DISABLE)
  { 
    RCC->APB1ENR |= RCC_APB1Periph;
  }
  else
  { 
    RCC->APB1ENR &= ~RCC_APB1Periph;
  }
}

#ifdef STM32F10X_CL

void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
{ 
  
  assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
  { 
    RCC->AHBRSTR |= RCC_AHBPeriph;
  }
  else
  { 
    RCC->AHBRSTR &= ~RCC_AHBPeriph;
  }
}
#endif  


void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
{ 
  
  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  if (NewState != DISABLE)
  { 
    RCC->APB2RSTR |= RCC_APB2Periph;
  }
  else
  { 
    RCC->APB2RSTR &= ~RCC_APB2Periph;
  }
}


void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
{ 
  
  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  if (NewState != DISABLE)
  { 
    RCC->APB1RSTR |= RCC_APB1Periph;
  }
  else
  { 
    RCC->APB1RSTR &= ~RCC_APB1Periph;
  }
}


void RCC_BackupResetCmd(FunctionalState NewState)
{ 
  
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
}


void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
{ 
  
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
}


void RCC_MCOConfig(uint8_t RCC_MCO)
{ 
  
  assert_param(IS_RCC_MCO(RCC_MCO));

  
  *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
}


FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
{ 
  uint32_t tmp = 0;
  uint32_t statusreg = 0;
  FlagStatus bitstatus = RESET;
  
  assert_param(IS_RCC_FLAG(RCC_FLAG));

  
  tmp = RCC_FLAG >> 5;
  if (tmp == 1)               
  { 
    statusreg = RCC->CR;
  }
  else if (tmp == 2)          
  { 
    statusreg = RCC->BDCR;
  }
  else                       
  { 
    statusreg = RCC->CSR;
  }

  
  tmp = RCC_FLAG & FLAG_Mask;
  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
  { 
    bitstatus = SET;
  }
  else
  { 
    bitstatus = RESET;
  }

  
  return bitstatus;
}


void RCC_ClearFlag(void)
{ 
  
  RCC->CSR |= CSR_RMVF_Set;
}


ITStatus RCC_GetITStatus(uint8_t RCC_IT)
{ 
  ITStatus bitstatus = RESET;
  
  assert_param(IS_RCC_GET_IT(RCC_IT));

  
  if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
  { 
    bitstatus = SET;
  }
  else
  { 
    bitstatus = RESET;
  }

  
  return  bitstatus;
}


void RCC_ClearITPendingBit(uint8_t RCC_IT)
{ 
  
  assert_param(IS_RCC_CLEAR_IT(RCC_IT));

  
  *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
}

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