1 开发环境

软件版本：vivado 2019.1

FPGA版本：xilinx K7 FPGA

2 遇到问题

1）使用vivado建立工程，添加代码、添加约束、综合、布局布线，生成bit文件。

2）vivado 布局布线时工程报错，错误提示如下：

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets ADC_top_inst/adc_group[0].ads1675_top_inst/diff_to_single_inst0/adc_user_clk] >
ADC_top_inst/adc_group[0].ads1675_top_inst/diff_to_single_inst0/IBUFDS_inst1 (IBUFDS.O) is locked to IOB_X0Y36
and ADC_top_inst/adc_group[0].ads1675_top_inst/adc_user_clk_BUFG_inst (BUFG.I) is provisionall