前言

最近一直没有时间，最想做的“设计一门完备又有效的ruby类语言”这种事也没时间做！由于这个EDA有课，所以就先练习下！

VSCode编辑

下载一个VHDL插件就好，VSCode的界面看着很舒服

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--注释
entity adder_8bits is 
    port(
        A,B : in std_logic_vector(7 downto 0);
        CIN : in std_logic;
        COUT: out std_logic;
        DOUT: out std_logic_vector(7 downto 0)
    );
    end entity adder_8bits;


architecture BIG of adder_8bits is
    signal DATA : std_logic_vector(8 downto 0);
    begin
        DATA <= ('0'&A)+('0'&B)+("00000000"&CIN);
        COUT <= DATA(8);
		DOUT <= DATA(7 downto 0);
    end architecture BIG;

Quartus II编译

输入代码，选择Processing > start > Analysis & Elaboration

查看RTL电路图

Tools > Netlist viewer > RTL viewer