一、设计要求
本设计是在做ov7670摄像头采集数据流时，以SDRAM作为缓存使用，因此这里才使用SDRAM对其进行介绍和设计。
在对ov7670摄像头数据存储时，SDRAM采用冲突读和冲突写模式，cas延时为3，冲突长度为8。能正常对不同地址、不同bank进行读写。
二、设计思路
程序主体框架采用状态机编写，主要有以下几个状态：空状态（NOP）、预充电状态（PRECHARGE）、刷新状态（REF）、加载模式寄存器状态（MODE）、空闲状态（IDLE）、激活状态（ACTIVE）、写状态（WRITE）、读状态（READ）。
其状态转移图如图所示：
状态机里的初始化操作包括空状态、预充电状态、刷新状态和加载模式寄存机状态，按照前面所讲的初始化过程进行初始化，初始化完成后进入空闲状态，在空间状态时可以进行读或写操作，进入激活状态，将对应的bank激活后才能进行读写，读写完成后进入预充电状态，然后再回到空闲状态。在空闲状态也会进入自刷新状态，每64ms要刷新4096次。这样，整个状态机框架就出来了。
三、设计实现
接口信号设置：
| 信号名称 | 位宽 | 方向 | 说明 |
| clk | 1 | I | 输入时钟信号100MHZ |
| rst_n | 1 | I | 复位信号 |
| wr_en | 1 | I | 写使能信号 |
| wr_data | 16 | I | 写数据 |
| rd_en | 1 | I | 读使能信号 |
| bank_addr | 2 | I | bank地址 |
| row_addr | 12 | I | 行地址 |
| col_addr | 9 | I | 列地址 |
| rd_data | 16 | O | 读出的数据 |
| rd_data_vld | 1 | O | 读出数据有效位 |
| wr_data_vld | 1 | O | 写入数据有效位 |
| wdata_done | 1 | O | 写数据结束标志 |
| rdata_done | 1 | O | 读数据结束标志 |
| sdram_clk | 1 | O | SDRAM时钟信号 |
| sdram_commond | 4 | O | {cs,ras,cas,we}四个信号组合 |
| sdram_cke | 1 | O | 时钟使能信号 |
| sdram_dqm | 2 | O | 数据线屏蔽信号 |
| sdram_addr | 12 | O | SDRAM地址线 |
| sdram_bank | 2 | O | SDRAM bank选取 |
| sdram_dq | 16 | IO | SDRAM数据输出输入总线 |
代码如下：代码具体细节部分不做说明，按照自己需求进行编写。
// Company :
// Engineer :
// -----------------------------------------------------------------------------
// https://blog.csdn.net/qq_33231534 PHF's CSDN blog
// -----------------------------------------------------------------------------
// Create Date : 2020-09-18 14:20:22
// Revise Data : 2020-09-20 15:30:16
// File Name : SDRAM_control.v
// Target Devices : XC7Z015-CLG485-2
// Tool Versions : Vivado 2019.2
// Revision : V1.1
// Editor : sublime text3, tab size (4)
// Description : SDRAM控制器，支持读写冲突长度为8，cas为3
module SDRAM_control(
input clk ,//100MHZ
input rst_n ,//复位
input wr_en ,//写使能信号
input [15:0] wr_data ,//写数据
input rd_en ,//读使能信号
input [1:0] bank_addr ,//bank地址
input [11:0] row_addr ,//行地址
input [8:0] col_addr ,//列地址
output reg [15:0] rd_data ,//读出的数据
output reg rd_data_vld ,//读出数据有效位
output wire wr_data_vld ,//写入数据有效位
output wire wdata_done ,//写数据结束标志
output wire rdata_done ,//读数据结束标志
output wire sdram_clk ,//SDRAM时钟信号
output reg [3:0] sdram_commond ,//{cs,ras,cas,we}
output wire sdram_cke ,//时钟使能信号
output reg [1:0] sdram_dqm ,//数据线屏蔽信号
output reg [11:0] sdram_addr ,//SDRAM地址线
output reg [1:0] sdram_bank ,//SDRAM bank选取
inout wire[15:0] sdram_dq //SDRAM数据输出输入总线
);
//延时
localparam TWAIT_200us = 15'd20000 ;//上电等待时间
localparam TRP = 2'd3 ;//预充电周期
localparam TRC = 4'd10 ;//自刷新周期
localparam TRSC = 2'd3 ;//加载模式寄存器周期
localparam TRCD = 2'd2 ;//激活命令周期
localparam TREAD_11 = 4'd11 ;//burst=8,cas=3
localparam TWRITE_8 = 4'd8 ;//burst=8
localparam AUTO_REF_TIME= 11'd1562 ;
//状态
localparam NOP = 3'd0 ;
localparam PRECHARGE = 3'd1 ;
localparam REF = 3'd2 ;
localparam MODE = 3'd3 ;
localparam IDLE = 3'd4 ;
localparam ACTIVE = 3'd5 ;
localparam WRITE = 3'd6 ;
localparam READ = 3'd7 ;
//操作命令
localparam NOP_CMD = 4'b0111 ;
localparam PRECHARGE_CMD= 4'b0010 ;
localparam REF_CMD = 4'b0001 ;
localparam MODE_CMD = 4'b0000 ;
localparam ACTIVE_CMD = 4'b0011 ;
localparam WRITE_CMD = 4'b0100 ;
localparam READ_CMD = 4'b0101 ;
//初始化阶段地址线
localparam ALL_BANK = 12'b01_0_00_000_0_000;//预充电地址线
localparam MODE_CONFIG = 12'b00_0_00_011_0_011;//配置模式寄存器时地址线
wire nop_to_pre_start ;
wire pre_to_ref_start ;
wire pre_to_idle_start ;
wire ref_to_mode_start ;
wire ref_to_idle_start ;
wire ref_to_ref_start ;
wire mode_to_idle_start ;
wire idle_to_active_start ;
wire idle_to_ref_start ;
wire active_to_write_start ;
wire active_to_read_start ;
wire write_to_pre_start ;
wire read_to_pre_start ;
reg [2:0] state_c;
reg [2:0] state_n;
wire sdram_dq_en;
wire[15:0] sdram_dq_r;
reg rd_data_vld_ff0;
reg rd_data_vld_ff1;
reg rd_data_vld_ff2;
reg [10:0] auto_ref_cnt;
wire add_auto_ref_cnt;
wire end_auto_ref_cnt;
reg ref_req;
wire init_done;
reg init_flag;
reg [14:0] cnt0 ;
wire add_cnt0;
wire end_cnt0;
reg [14:0] x;
reg [3:0] ref_cnt1;
wire add_cnt1;
wire end_cnt1;
reg flag_rd;
reg flag_wr;
assign sdram_clk = ~clk;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state_c <= NOP;
end
else begin
state_c <= state_n;
end
end
always @(*)begin
case(state_c)
NOP :begin
if (nop_to_pre_start) begin
state_n = PRECHARGE;
end
else begin
state_n = state_c;
end
end
PRECHARGE:begin
if (pre_to_ref_start) begin
state_n = REF;
end
else if (pre_to_idle_start) begin
state_n = IDLE;
end
else begin
state_n = state_c;
end
end
REF:begin
if (ref_to_mode_start) begin
state_n = MODE;
end
else if (ref_to_idle_start) begin
state_n = IDLE;
end
else if (ref_to_ref_start) begin
state_n = REF;
end
else begin
state_n = state_c;
end
end
MODE:begin
if (mode_to_idle_start) begin
state_n = IDLE;
end
else begin
state_n =state_c;
end
end
IDLE:begin
if (idle_to_active_start) begin
state_n = ACTIVE;
end
else if (idle_to_ref_start) begin
state_n = REF;
end
else begin
state_n = state_c;
end
end
ACTIVE:begin
if (active_to_write_start) begin
state_n = WRITE;
end
else if (active_to_read_start) begin
state_n = READ;
end
else begin
state_n = state_c;
end
end
WRITE:begin
if(write_to_pre_start)begin
state_n = PRECHARGE;
end
else begin
state_n = state_c;
end
end
READ:begin
if (read_to_pre_start) begin
state_n = PRECHARGE;
end
else begin
state_n = state_c;
end
end
default:state_n = IDLE;
endcase
end
assign nop_to_pre_start = (state_c==NOP && end_cnt0);
assign pre_to_ref_start = (state_c==PRECHARGE && end_cnt0 && init_flag==1);
assign pre_to_idle_start = (state_c==PRECHARGE && end_cnt0 && init_flag==0);
assign ref_to_mode_start = (state_c==REF && init_flag==1 && end_cnt1);
assign ref_to_idle_start = (state_c==REF && init_flag==0 && end_cnt0);
assign ref_to_ref_start = (state_c==REF && init_flag==1 && end_cnt0 && ref_cnt1<7);
assign mode_to_idle_start = (state_c==MODE && init_flag==1 && end_cnt0);
assign idle_to_active_start = (state_c==IDLE && (wr_en || rd_en) && ref_req==0);
assign idle_to_ref_start = (state_c==IDLE && ref_req==1);
assign active_to_write_start = (state_c==ACTIVE && end_cnt0 && flag_wr);
assign active_to_read_start = (state_c==ACTIVE && end_cnt0 && flag_rd);
assign write_to_pre_start = (state_c==WRITE && end_cnt0);
assign read_to_pre_start = (state_c==READ && end_cnt0);
//命令控制字 sdram_commond = {CS,RAS,CAS,WE};
always @(posedge clk or negedge rst_n)begin
if (!rst_n) begin
sdram_commond <= NOP_CMD;
end
else if (nop_to_pre_start || write_to_pre_start || read_to_pre_start) begin
sdram_commond <= PRECHARGE_CMD;
end
else if (pre_to_ref_start || ref_to_ref_start || idle_to_ref_start) begin
sdram_commond <= REF_CMD;
end
else if (ref_to_mode_start) begin
sdram_commond <= MODE_CMD;
end
else if (idle_to_active_start) begin
sdram_commond <= ACTIVE_CMD;
end
else if (active_to_write_start) begin
sdram_commond <= WRITE_CMD;
end
else if (active_to_read_start) begin
sdram_commond <= READ_CMD;
end
else begin
sdram_commond <= NOP_CMD;
end
end
//cke信号保持拉高
assign sdram_cke = 1;
//dqm信号
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
sdram_dqm <= 2'b11;
end
else if(init_done)begin
sdram_dqm <= 2'b00;
end
end
//地址线
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
sdram_addr <= 12'b0;
end
else if(nop_to_pre_start || write_to_pre_start || read_to_pre_start)begin
sdram_addr <= ALL_BANK;
end
else if(ref_to_mode_start)begin
sdram_addr <= MODE_CONFIG;
end
else if(idle_to_active_start)begin
sdram_addr <= row_addr;
end
else if (active_to_read_start || active_to_write_start) begin
sdram_addr <= {3'b000,col_addr};
end
else begin
sdram_addr <= 12'b0;
end
end
//sdram_bank
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
sdram_bank <= 2'b00;
end
else if (idle_to_active_start || active_to_write_start || active_to_read_start) begin
sdram_bank <= bank_addr;
end
else begin
sdram_bank <= 2'b00;
end
end
//sdram_dq
assign sdram_dq_en = (state_c==WRITE) ? 1'b1 : 1'b0;
assign sdram_dq = sdram_dq_en ? sdram_dq_r : 16'hzzzz;
assign sdram_dq_r = wr_data;
assign wr_data_vld = state_c==WRITE;
assign wdata_done = write_to_pre_start;
assign rdata_done = read_to_pre_start;
always @(posedge clk or negedge rst_n)begin
if (!rst_n) begin
rd_data <= 16'd0;
end
else if (state_c==READ) begin
rd_data <= sdram_dq;
end
end
//读有效标志
always @(posedge clk or negedge rst_n)begin
if (!rst_n) begin
rd_data_vld_ff0 <= 0;
end
else if (active_to_read_start) begin
rd_data_vld_ff0 <= 1;
end
else if (state_c==READ && cnt0==TREAD_11-4) begin
rd_data_vld_ff0 <= 0;
end
end
always @(posedge clk or negedge rst_n)begin
if (!rst_n) begin
rd_data_vld_ff1 <= 0;
rd_data_vld_ff2 <= 0;
rd_data_vld <= 0;
end
else begin
rd_data_vld_ff1 <= rd_data_vld_ff0;
rd_data_vld_ff2 <= rd_data_vld_ff1;
rd_data_vld <= rd_data_vld_ff2;
end
end
//刷新请求计数
always @(posedge clk or negedge rst_n)begin
if (!rst_n) begin
auto_ref_cnt <= 0;
end
else if (add_auto_ref_cnt) begin
if (end_auto_ref_cnt) begin
auto_ref_cnt <= 0;
end
else begin
auto_ref_cnt <= auto_ref_cnt + 1'b1;
end
end
end
assign add_auto_ref_cnt = init_flag==0;
assign end_auto_ref_cnt = (add_auto_ref_cnt && auto_ref_cnt==AUTO_REF_TIME-1);
//ref_req 刷新请求
always @(posedge clk or negedge rst_n)begin
if (!rst_n) begin
ref_req <= 0;
end
else if (end_auto_ref_cnt) begin
ref_req <= 1;
end
else if (state_c==IDLE && ref_req==1) begin
ref_req <= 0;
end
end
//初始化标志
assign init_done = (state_c==MODE && end_cnt0);
always @(posedge clk or negedge rst_n)begin
if (!rst_n) begin
init_flag <= 1;
end
else if (init_done) begin
init_flag <= 0;
end
end
always @(posedge clk or negedge rst_n)begin
if (!rst_n) begin
cnt0 <= 0;
end
else if (add_cnt0) begin
if (end_cnt0) begin
cnt0 <= 0;
end
else begin
cnt0 <= cnt0 + 1'b1;
end
end
end
assign add_cnt0 = state_c!=IDLE;
assign end_cnt0 = add_cnt0 && cnt0==x-1'b1;
always @(*)begin
case(state_c)
NOP : x = TWAIT_200us;
PRECHARGE : x = TRP;
REF : x = TRC;
MODE : x = TRSC;
ACTIVE : x = TRCD;
WRITE : x = TWRITE_8;
READ : x = TREAD_11;
default : x = 0;
endcase
end
//初始化自刷新8个周期计数
always @(posedge clk or negedge rst_n)begin
if (!rst_n) begin
ref_cnt1 <= 0;
end
else if (add_cnt1) begin
if (end_cnt1) begin
ref_cnt1 <= 0;
end
else begin
ref_cnt1 <= ref_cnt1 + 1'b1;
end
end
end
assign add_cnt1 = (state_c==REF && init_flag==1 && end_cnt0);
assign end_cnt1 = (add_cnt1 && ref_cnt1== 8-1);
//读写信号标志
always @(posedge clk or negedge rst_n)begin
if (!rst_n) begin
flag_rd <= 0;
end
else if (state_c==IDLE && rd_en && ref_req==0) begin
flag_rd <= 1;
end
else if (pre_to_idle_start && flag_rd==1) begin
flag_rd <= 0;
end
end
always @(posedge clk or negedge rst_n)begin
if (!rst_n) begin
flag_wr <= 0;
end
else if (state_c==IDLE && wr_en && rd_en==0 && ref_req==0) begin //读优先级高于写优先级
flag_wr <= 1;
end
else if (pre_to_idle_start && flag_wr==1) begin
flag_wr <= 0;
end
end
endmodule
四、仿真测试
这里使用SDRAM的仿真模型是开源骚客的资料里的，小梅哥用的镁光的SDRAM仿真模型我没有找到。
仿真模型代码如下供有需要的人使用：
//2004-03-04 陈乃奎 修改原程序中将BANK的数据转存入TXT文件的格式
//2004-03-16 陈乃奎 修改SDRAM 的初始化数据
//2004/04/06 陈乃奎 将SDRAM的操作命令以字符形式表示，以便用MODELSIM监视
//2004/04/19 陈乃奎 修改参数 parameter tAC = 8;
//2010/09/17 罗瑶 修改sdram的大小，数据位宽，dqm宽度;
`timescale 1ns / 1ps
module sdram_model_plus (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm,Debug);
parameter addr_bits = 11;
parameter data_bits = 32;
parameter col_bits = 8;
parameter mem_sizes = 1048576*2-1;//1 Meg
inout [data_bits - 1 : 0] Dq;
input [addr_bits - 1 : 0] Addr;
input [1 : 0] Ba;
input Clk;
input Cke;
input Cs_n;
input Ras_n;
input Cas_n;
input We_n;
input [3 : 0] Dqm; //高低各8bit
//added by xzli
input Debug;
reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];//存储器类型数据
reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline
reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline
reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline
reg [3 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline
reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
reg [addr_bits - 1 : 0] Mode_reg;
reg [data_bits - 1 : 0] Dq_reg, Dq_dqm;
reg [col_bits - 1 : 0] Col_temp, Burst_counter;
reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate
reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge
reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command
reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks)
reg Auto_precharge [0 : 3]; // RW AutoPrecharge (Bank)
reg Read_precharge [0 : 3]; // R AutoPrecharge
reg Write_precharge [0 : 3]; // W AutoPrecharge
integer Count_precharge [0 : 3]; // RW AutoPrecharge (Counter)
reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge
reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge
reg Data_in_enable;
reg Data_out_enable;
reg [1 : 0] Bank, Previous_bank;
reg [addr_bits - 1 : 0] Row;
reg [col_bits - 1 : 0] Col, Col_brst;
// Internal system clock
reg CkeZ, Sys_clk;
reg [21:0] dd;
// Commands Decode
wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;
wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n;
wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n;
wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n;
wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n;
wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n;
wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n;
// Burst Length Decode
wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0];
wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
// CAS Latency Decode
wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4];
wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];
// Write Burst Mode
wire Write_burst_mode = Mode_reg[9];
wire Debug; // Debug messages : 1 = On; 0 = Off
wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ
reg [31:0] mem_d;
event sdram_r,sdram_w,compare;
assign Dq = Dq_reg; // DQ buffer
// Commands Operation
`define ACT 0
`define NOP 1
`define READ 2
`define READ_A 3
`define WRITE 4
`define WRITE_A 5
`define PRECH 6
`define A_REF 7
`define BST 8
`define LMR 9
// // Timing Parameters for -75 (PC133) and CAS Latency = 2
// parameter tAC = 8; //test 6.5
// parameter tHZ = 7.0;
// parameter tOH = 2.7;
// parameter tMRD = 2.0; // 2 Clk Cycles
// parameter tRAS = 44.0;
// parameter tRC = 66.0;
// parameter tRCD = 20.0;
// parameter tRP = 20.0;
// parameter tRRD = 15.0;
// parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
// parameter tWRp = 0.0; // A2 Version - Precharge mode only (15 ns)
// Timing Parameters for -7 (PC143) and CAS Latency = 3
parameter tAC = 6.5; //test 6.5
parameter tHZ = 5.5;
parameter tOH = 2;
parameter tMRD = 2.0; // 2 Clk Cycles
parameter tRAS = 48.0;
parameter tRC = 70.0;
parameter tRCD = 20.0;
parameter tRP = 20.0;
parameter tRRD = 14.0;
parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
parameter tWRp = 0.0; // A2 Version - Precharge mode only (15 ns)
// Timing Check variable
integer MRD_chk;
integer WR_counter [0 : 3];
time WR_chk [0 : 3];
time RC_chk, RRD_chk;
time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
integer test_file;
/
initial_sdram(0);
end
task initial_sdram;
input data_sign;
reg [3:0] data_sign;
for(dd=0;dd<=mem_sizes;dd=dd+1)
begin
mem_d = {data_sign,data_sign,data_sign,data_sign,data_sign,data_sign,data_sign,data_sign};
if(data_bits==16)
begin
Bank0[dd]=mem_d[15:0];
Bank1[dd]=mem_d[15:0];
Bank2[dd]=mem_d[15:0];
Bank3[dd]=mem_d[15:0];
end
else if(data_bits==32)
begin
Bank0[dd]=mem_d[31:0];
Bank1[dd]=mem_d[31:0];
Bank2[dd]=mem_d[31:0];
Bank3[dd]=mem_d[31:0];
end
end
endtask
// System clock generator
always
begin
@(posedge Clk)
begin
Sys_clk = CkeZ;
CkeZ = Cke;
end
@(negedge Clk)
begin
Sys_clk = 1'b0;
end
end
always @ (posedge Sys_clk) begin
// Internal Commamd Pipelined
Command[0] = Command[1];
Command[1] = Command[2];
Command[2] = Command[3];
Command[3] = `NOP;
Col_addr[0] = Col_addr[1];
Col_addr[1] = Col_addr[2];
Col_addr[2] = Col_addr[3];
Col_addr[3] = {col_bits{1'b0}};
Bank_addr[0] = Bank_addr[1];
Bank_addr[1] = Bank_addr[2];
Bank_addr[2] = Bank_addr[3];
Bank_addr[3] = 2'b0;
Bank_precharge[0] = Bank_precharge[1];
Bank_precharge[1] = Bank_precharge[2];
Bank_precharge[2] = Bank_precharge[3];
Bank_precharge[3] = 2'b0;
A10_precharge[0] = A10_precharge[1];
A10_precharge[1] = A10_precharge[2];
A10_precharge[2] = A10_precharge[3];
A10_precharge[3] = 1'b0;
// Dqm pipeline for Read
Dqm_reg0 = Dqm_reg1;
Dqm_reg1 = Dqm;
// Read or Write with Auto Precharge Counter
if (Auto_precharge[0] == 1'b1) begin
Count_precharge[0] = Count_precharge[0] + 1;
end
if (Auto_precharge[1] == 1'b1) begin
Count_precharge[1] = Count_precharge[1] + 1;
end
if (Auto_precharge[2] == 1'b1) begin
Count_precharge[2] = Count_precharge[2] + 1;
end
if (Auto_precharge[3] == 1'b1) begin
Count_precharge[3] = Count_precharge[3] + 1;
end
// tMRD Counter
MRD_chk = MRD_chk + 1;
// tWR Counter for Write
WR_counter[0] = WR_counter[0] + 1;
WR_counter[1] = WR_counter[1] + 1;
WR_counter[2] = WR_counter[2] + 1;
WR_counter[3] = WR_counter[3] + 1;
// Auto Refresh
if (Aref_enable == 1'b1) begin
if (Debug) $display ("at time %t AREF : Auto Refresh", $time);
// Auto Refresh to Auto Refresh
if (($time - RC_chk < tRC)&&Debug) begin
$display ("at time %t ERROR: tRC violation during Auto Refresh", $time);
end
// Precharge to Auto Refresh
if (($time - RP_chk0 < tRP || $time - RP_chk1 < tRP || $time - RP_chk2 < tRP || $time - RP_chk3 < tRP)&&Debug) begin
$display ("at time %t ERROR: tRP violation during Auto Refresh", $time);
end
// Precharge to Refresh
if (Pc_b0 == 1'b0 || Pc_b1 == 1'b0 || Pc_b2 == 1'b0 || Pc_b3 == 1'b0) begin
$display ("at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);
end
// Record Current tRC time
RC_chk = $time;
end
// Load Mode Register
if (Mode_reg_enable == 1'b1) begin
// Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode
if (Pc_b0 == 1'b1 && Pc_b1 == 1'b1 && Pc_b2 == 1'b1 && Pc_b3 == 1'b1) begin
Mode_reg = Addr;
if (Debug) begin
$display ("at time %t LMR : Load Mode Register", $time);
// CAS Latency
if (Addr[6 : 4] == 3'b010)
$display (" CAS Latency = 2");
else if (Addr[6 : 4] == 3'b011)
$display (" CAS Latency = 3");
else
$display (" CAS Latency = Reserved");
// Burst Length
if (Addr[2 : 0] == 3'b000)
$display (" Burst Length = 1");
else if (Addr[2 : 0] == 3'b001)
$display (" Burst Length = 2");
else if (Addr[2 : 0] == 3'b010)
$display (" Burst Length = 4");
else if (Addr[2 : 0] == 3'b011)
$display (" Burst Length = 8");
else if (Addr[3 : 0] == 4'b0111)
$display (" Burst Length = Full");
else
$display (" Burst Length = Reserved");
// Burst Type
if (Addr[3] == 1'b0)
$display (" Burst Type = Sequential");
else if (Addr[3] == 1'b1)
$display (" Burst Type = Interleaved");
else
$display (" Burst Type = Reserved");
// Write Burst Mode
if (Addr[9] == 1'b0)
$display (" Write Burst Mode = Programmed Burst Length");
else if (Addr[9] == 1'b1)
$display (" Write Burst Mode = Single Location Access");
else
$display (" Write Burst Mode = Reserved");
end
end else begin
$display ("at time %t ERROR: all banks must be Precharge before Load Mode Register", $time);
end
// REF to LMR
if ($time - RC_chk < tRC) begin
$display ("at time %t ERROR: tRC violation during Load Mode Register", $time);
end
// LMR to LMR
if (MRD_chk < tMRD) begin
$display ("at time %t ERROR: tMRD violation during Load Mode Register", $time);
end
MRD_chk = 0;
end
// Active Block (Latch Bank Address and Row Address)
if (Active_enable == 1'b1) begin
if (Ba == 2'b00 && Pc_b0 == 1'b1) begin
{Act_b0, Pc_b0} = 2'b10;
B0_row_addr = Addr [addr_bits - 1 : 0];
RCD_chk0 = $time;
RAS_chk0 = $time;
if (Debug) $display ("at time %t ACT : Bank = 0 Row = %d", $time, Addr);
// Precharge to Activate Bank 0
if ($time - RP_chk0 < tRP) begin
$display ("at time %t ERROR: tRP violation during Activate bank 0", $time);
end
end else if (Ba == 2'b01 && Pc_b1 == 1'b1) begin
{Act_b1, Pc_b1} = 2'b10;
B1_row_addr = Addr [addr_bits - 1 : 0];
RCD_chk1 = $time;
RAS_chk1 = $time;
if (Debug) $display ("at time %t ACT : Bank = 1 Row = %d", $time, Addr);
// Precharge to Activate Bank 1
if ($time - RP_chk1 < tRP) begin
$display ("at time %t ERROR: tRP violation during Activate bank 1", $time);
end
end else if (Ba == 2'b10 && Pc_b2 == 1'b1) begin
{Act_b2, Pc_b2} = 2'b10;
B2_row_addr = Addr [addr_bits - 1 : 0];
RCD_chk2 = $time;
RAS_chk2 = $time;
if (Debug) $display ("at time %t ACT : Bank = 2 Row = %d", $time, Addr);
// Precharge to Activate Bank 2
if ($time - RP_chk2 < tRP) begin
$display ("at time %t ERROR: tRP violation during Activate bank 2", $time);
end
end else if (Ba == 2'b11 && Pc_b3 == 1'b1) begin
{Act_b3, Pc_b3} = 2'b10;
B3_row_addr = Addr [addr_bits - 1 : 0];
RCD_chk3 = $time;
RAS_chk3 = $time;
if (Debug) $display ("at time %t ACT : Bank = 3 Row = %d", $time, Addr);
// Precharge to Activate Bank 3
if ($time - RP_chk3 < tRP) begin
$display ("at time %t ERROR: tRP violation during Activate bank 3", $time);
end
end else if (Ba == 2'b00 && Pc_b0 == 1'b0) begin
$display ("at time %t ERROR: Bank 0 is not Precharged.", $time);
end else if (Ba == 2'b01 && Pc_b1 == 1'b0) begin
$display ("at time %t ERROR: Bank 1 is not Precharged.", $time);
end else if (Ba == 2'b10 && Pc_b2 == 1'b0) begin
$display ("at time %t ERROR: Bank 2 is not Precharged.", $time);
end else if (Ba == 2'b11 && Pc_b3 == 1'b0) begin
$display ("at time %t ERROR: Bank 3 is not Precharged.", $time);
end
// Active Bank A to Active Bank B
if ((Previous_bank != Ba) && ($time - RRD_chk < tRRD)) begin
$display ("at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba);
end
// Load Mode Register to Active
if (MRD_chk < tMRD ) begin
$display ("at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba);
end
// Auto Refresh to Activate
if (($time - RC_chk < tRC)&&Debug) begin
$display ("at time %t ERROR: tRC violation during Activate bank = %d", $time, Ba);
end
// Record variables for checking violation
RRD_chk = $time;
Previous_bank = Ba;
end
// Precharge Block
if (Prech_enable == 1'b1) begin
if (Addr[10] == 1'b1) begin
{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b1111;
{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;
RP_chk0 = $time;
RP_chk1 = $time;
RP_chk2 = $time;
RP_chk3 = $time;
if (Debug) $display ("at time %t PRE : Bank = ALL",$time);
// Activate to Precharge all banks
if (($time - RAS_chk0 < tRAS) || ($time - RAS_chk1 < tRAS) ||
($time - RAS_chk2 < tRAS) || ($time - RAS_chk3 < tRAS)) begin
$display ("at time %t ERROR: tRAS violation during Precharge all bank", $time);
end
// tWR violation check for write
if (($time - WR_chk[0] < tWRp) || ($time - WR_chk[1] < tWRp) ||
($time - WR_chk[2] < tWRp) || ($time - WR_chk[3] < tWRp)) begin
$display ("at time %t ERROR: tWR violation during Precharge all bank", $time);
end
end else if (Addr[10] == 1'b0) begin
if (Ba == 2'b00) begin
{Pc_b0, Act_b0} = 2'b10;
RP_chk0 = $time;
if (Debug) $display ("at time %t PRE : Bank = 0",$time);
// Activate to Precharge Bank 0
if ($time - RAS_chk0 < tRAS) begin
$display ("at time %t ERROR: tRAS violation during Precharge bank 0", $time);
end
end else if (Ba == 2'b01) begin
{Pc_b1, Act_b1} = 2'b10;
RP_chk1 = $time;
if (Debug) $display ("at time %t PRE : Bank = 1",$time);
// Activate to Precharge Bank 1
if ($time - RAS_chk1 < tRAS) begin
$display ("at time %t ERROR: tRAS violation during Precharge bank 1", $time);
end
end else if (Ba == 2'b10) begin
{Pc_b2, Act_b2} = 2'b10;
RP_chk2 = $time;
if (Debug) $display ("at time %t PRE : Bank = 2",$time);
// Activate to Precharge Bank 2
if ($time - RAS_chk2 < tRAS) begin
$display ("at time %t ERROR: tRAS violation during Precharge bank 2", $time);
end
end else if (Ba == 2'b11) begin
{Pc_b3, Act_b3} = 2'b10;
RP_chk3 = $time;
if (Debug) $display ("at time %t PRE : Bank = 3",$time);
// Activate to Precharge Bank 3
if ($time - RAS_chk3 < tRAS) begin
$display ("at time %t ERROR: tRAS violation during Precharge bank 3", $time);
end
end
// tWR violation check for write
if ($time - WR_chk[Ba] < tWRp) begin
$display ("at time %t ERROR: tWR violation during Precharge bank %d", $time, Ba);
end
end
// Terminate a Write Immediately (if same bank or all banks)
if (Data_in_enable == 1'b1 && (Bank == Ba || Addr[10] == 1'b1)) begin
Data_in_enable = 1'b0;
end
// Precharge Command Pipeline for Read
if (Cas_latency_3 == 1'b1) begin
Command[2] = `PRECH;
Bank_precharge[2] = Ba;
A10_precharge[2] = Addr[10];
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `PRECH;
Bank_precharge[1] = Ba;
A10_precharge[1] = Addr[10];
end
end
// Burst terminate
if (Burst_term == 1'b1) begin
// Terminate a Write Immediately
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
// Terminate a Read Depend on CAS Latency
if (Cas_latency_3 == 1'b1) begin
Command[2] = `BST;
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `BST;
end
if (Debug) $display ("at time %t BST : Burst Terminate",$time);
end
// Read, Write, Column Latch
if (Read_enable == 1'b1 || Write_enable == 1'b1) begin
// Check to see if bank is open (ACT)
if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
(Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
$display("at time %t ERROR: Cannot Read or Write - Bank %d is not Activated", $time, Ba);
end
// Activate to Read or Write
if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD))
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 0", $time);
if ((Ba == 2'b01) && ($time - RCD_chk1 < tRCD))
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 1", $time);
if ((Ba == 2'b10) && ($time - RCD_chk2 < tRCD))
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 2", $time);
if ((Ba == 2'b11) && ($time - RCD_chk3 < tRCD))
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 3", $time);
// Read Command
if (Read_enable == 1'b1) begin
// CAS Latency pipeline
if (Cas_latency_3 == 1'b1) begin
if (Addr[10] == 1'b1) begin
Command[2] = `READ_A;
end else begin
Command[2] = `READ;
end
Col_addr[2] = Addr;
Bank_addr[2] = Ba;
end else if (Cas_latency_2 == 1'b1) begin
if (Addr[10] == 1'b1) begin
Command[1] = `READ_A;
end else begin
Command[1] = `READ;
end
Col_addr[1] = Addr;
Bank_addr[1] = Ba;
end
// Read interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
// Write Command
end else if (Write_enable == 1'b1) begin
if (Addr[10] == 1'b1) begin
Command[0] = `WRITE_A;
end else begin
Command[0] = `WRITE;
end
Col_addr[0] = Addr;
Bank_addr[0] = Ba;
// Write interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
// Write interrupt Read (terminate Read immediately)
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
// Interrupting a Write with Autoprecharge
if (Auto_precharge[Bank] == 1'b1 && Write_precharge[Bank] == 1'b1) begin
RW_interrupt_write[Bank] = 1'b1;
if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, Bank);
end
// Interrupting a Read with Autoprecharge
if (Auto_precharge[Bank] == 1'b1 && Read_precharge[Bank] == 1'b1) begin
RW_interrupt_read[Bank] = 1'b1;
if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, Bank);
end
// Read or Write with Auto Precharge
if (Addr[10] == 1'b1) begin
Auto_precharge[Ba] = 1'b1;
Count_precharge[Ba] = 0;
if (Read_enable == 1'b1) begin
Read_precharge[Ba] = 1'b1;
end else if (Write_enable == 1'b1) begin
Write_precharge[Ba] = 1'b1;
end
end
end
// Read with Auto Precharge Calculation
// The device start internal precharge:
// 1. CAS Latency - 1 cycles before last burst
// and 2. Meet minimum tRAS requirement
// or 3. Interrupt by a Read or Write (with or without AutoPrecharge)
if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin
if ((($time - RAS_chk0 >= tRAS) && // Case 2
((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 1
(Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
(RW_interrupt_read[0] == 1'b1)) begin // Case 3
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
Auto_precharge[0] = 1'b0;
Read_precharge[0] = 1'b0;
RW_interrupt_read[0] = 1'b0;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
end
end
if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin
if ((($time - RAS_chk1 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
(RW_interrupt_read[1] == 1'b1)) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
Auto_precharge[1] = 1'b0;
Read_precharge[1] = 1'b0;
RW_interrupt_read[1] = 1'b0;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
end
end
if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin
if ((($time - RAS_chk2 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
(RW_interrupt_read[2] == 1'b1)) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
Auto_precharge[2] = 1'b0;
Read_precharge[2] = 1'b0;
RW_interrupt_read[2] = 1'b0;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
end
end
if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin
if ((($time - RAS_chk3 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
(RW_interrupt_read[3] == 1'b1)) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
Auto_precharge[3] = 1'b0;
Read_precharge[3] = 1'b0;
RW_interrupt_read[3] = 1'b0;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
end
end
// Internal Precharge or Bst
if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks
if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
end else if (Command[0] == `BST) begin // BST terminate a read to current bank
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
if (Data_out_enable == 1'b0) begin
Dq_reg <= #tOH {data_bits{1'bz}};
end
// Detect Read or Write command
if (Command[0] == `READ || Command[0] == `READ_A) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
if (Bank_addr[0] == 2'b00) begin
Row = B0_row_addr;
end else if (Bank_addr[0] == 2'b01) begin
Row = B1_row_addr;
end else if (Bank_addr[0] == 2'b10) begin
Row = B2_row_addr;
end else if (Bank_addr[0] == 2'b11) begin
Row = B3_row_addr;
end
Burst_counter = 0;
Data_in_enable = 1'b0;
Data_out_enable = 1'b1;
end else if (Command[0] == `WRITE || Command[0] == `WRITE_A) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
if (Bank_addr[0] == 2'b00) begin
Row = B0_row_addr;
end else if (Bank_addr[0] == 2'b01) begin
Row = B1_row_addr;
end else if (Bank_addr[0] == 2'b10) begin
Row = B2_row_addr;
end else if (Bank_addr[0] == 2'b11) begin
Row = B3_row_addr;
end
Burst_counter = 0;
Data_in_enable = 1'b1;
Data_out_enable = 1'b0;
end
// DQ buffer (Driver/Receiver)
if (Data_in_enable == 1'b1) begin // Writing Data to Memory
// Array buffer
if (Bank == 2'b00) Dq_dqm [data_bits - 1 : 0] = Bank0 [{Row, Col}];
if (Bank == 2'b01) Dq_dqm [data_bits - 1 : 0] = Bank1 [{Row, Col}];
if (Bank == 2'b10) Dq_dqm [data_bits - 1 : 0] = Bank2 [{Row, Col}];
if (Bank == 2'b11) Dq_dqm [data_bits - 1 : 0] = Bank3 [{Row, Col}];
// Dqm operation
if (Dqm[0] == 1'b0) Dq_dqm [ 7 : 0] = Dq [ 7 : 0];
if (Dqm[1] == 1'b0) Dq_dqm [15 : 8] = Dq [15 : 8];
//if (Dqm[2] == 1'b0) Dq_dqm [23 : 16] = Dq [23 : 16];
// if (Dqm[3] == 1'b0) Dq_dqm [31 : 24] = Dq [31 : 24];
// Write to memory
if (Bank == 2'b00) Bank0 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0];
if (Bank == 2'b01) Bank1 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0];
if (Bank == 2'b10) Bank2 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0];
if (Bank == 2'b11) Bank3 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0];
if (Bank == 2'b11 && Row==10'h3 && Col[7:4]==4'h4)
$display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
//$fdisplay(test_file,"bank:%h row:%h col:%h write:%h",Bank,Row,Col,Dq_dqm);
// Output result
if (Dqm == 4'b1111) begin
if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
end else begin
if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_dqm, Dqm);
// Record tWR time and reset counter
WR_chk [Bank] = $time;
WR_counter [Bank] = 0;
end
// Advance burst counter subroutine
#tHZ Burst;
end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory
//$display("%h , %h, %h",Bank0,Row,Col);
// Array buffer
if (Bank == 2'b00) Dq_dqm [data_bits - 1 : 0] = Bank0 [{Row, Col}];
if (Bank == 2'b01) Dq_dqm [data_bits - 1 : 0] = Bank1 [{Row, Col}];
if (Bank == 2'b10) Dq_dqm [data_bits - 1 : 0] = Bank2 [{Row, Col}];
if (Bank == 2'b11) Dq_dqm [data_bits - 1 : 0] = Bank3 [{Row, Col}];
// Dqm operation
if (Dqm_reg0[0] == 1'b1) Dq_dqm [ 7 : 0] = 8'bz;
if (Dqm_reg0[1] == 1'b1) Dq_dqm [15 : 8] = 8'bz;
if (Dqm_reg0[2] == 1'b1) Dq_dqm [23 : 16] = 8'bz;
if (Dqm_reg0[3] == 1'b1) Dq_dqm [31 : 24] = 8'bz;
// Display result
Dq_reg [data_bits - 1 : 0] = #tAC Dq_dqm [data_bits - 1 : 0];
if (Dqm_reg0 == 4'b1111) begin
if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
end else begin
if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_reg, Dqm_reg0);
end
// Advance burst counter subroutine
Burst;
end
end
// Write with Auto Precharge Calculation
// The device start internal precharge:
// 1. tWR Clock after last burst
// and 2. Meet minimum tRAS requirement
// or 3. Interrupt by a Read or Write (with or without AutoPrecharge)
always @ (WR_counter[0]) begin
if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin
if ((($time - RAS_chk0 >= tRAS) && // Case 2
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 1
(Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) ||
(RW_interrupt_write[0] == 1'b1 && WR_counter[0] >= 2)) begin // Case 3 (stop count when interrupt)
Auto_precharge[0] = 1'b0;
Write_precharge[0] = 1'b0;
RW_interrupt_write[0] = 1'b0;
#tWRa; // Wait for tWR
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
end
end
end
always @ (WR_counter[1]) begin
if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin
if ((($time - RAS_chk1 >= tRAS) &&
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) ||
(RW_interrupt_write[1] == 1'b1 && WR_counter[1] >= 2)) begin
Auto_precharge[1] = 1'b0;
Write_precharge[1] = 1'b0;
RW_interrupt_write[1] = 1'b0;
#tWRa; // Wait for tWR
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
end
end
end
always @ (WR_counter[2]) begin
if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin
if ((($time - RAS_chk2 >= tRAS) &&
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) ||
(RW_interrupt_write[2] == 1'b1 && WR_counter[2] >= 2)) begin
Auto_precharge[2] = 1'b0;
Write_precharge[2] = 1'b0;
RW_interrupt_write[2] = 1'b0;
#tWRa; // Wait for tWR
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
end
end
end
always @ (WR_counter[3]) begin
if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin
if ((($time - RAS_chk3 >= tRAS) &&
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) ||
(RW_interrupt_write[3] == 1'b1 && WR_counter[3] >= 2)) begin
Auto_precharge[3] = 1'b0;
Write_precharge[3] = 1'b0;
RW_interrupt_write[3] = 1'b0;
#tWRa; // Wait for tWR
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
end
end
end
task Burst;
begin
// Advance Burst Counter
Burst_counter = Burst_counter + 1;
// Burst Type
if (Mode_reg[3] == 1'b0) begin // Sequential Burst
Col_temp = Col + 1;
end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst
Col_temp[2] = Burst_counter[2] ^ Col_brst[2];
Col_temp[1] = Burst_counter[1] ^ Col_brst[1];
Col_temp[0] = Burst_counter[0] ^ Col_brst[0];
end
// Burst Length
if (Burst_length_2) begin // Burst Length = 2
Col [0] = Col_temp [0];
end else if (Burst_length_4) begin // Burst Length = 4
Col [1 : 0] = Col_temp [1 : 0];
end else if (Burst_length_8) begin // Burst Length = 8
Col [2 : 0] = Col_temp [2 : 0];
end else begin // Burst Length = FULL
Col = Col_temp;
end
// Burst Read Single Write
if (Write_burst_mode == 1'b1) begin
Data_in_enable = 1'b0;
end
// Data Counter
if (Burst_length_1 == 1'b1) begin
if (Burst_counter >= 1) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_2 == 1'b1) begin
if (Burst_counter >= 2) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_4 == 1'b1) begin
if (Burst_counter >= 4) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_8 == 1'b1) begin
if (Burst_counter >= 8) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end
end
endtask
//
integer sdram_data,sdram_mem;
reg [23:0] aa,cc;
reg [18:0] bb,ee;
always@(sdram_r)
begin
$display("Sdram dampout begin ",$realtime);
sdram_data=$fopen("sdram_data.txt");
for(aa=0;aa<4*(mem_sizes+1);aa=aa+1)
begin
bb=aa[18:0];
if(aa<=mem_sizes)
$fdisplay(sdram_data,"%0d %0h",aa,Bank0[bb]);
else if(aa<=2*mem_sizes+1)
$fdisplay(sdram_data,"%0d %0h",aa,Bank1[bb]);
else if(aa<=3*mem_sizes+2)
$fdisplay(sdram_data,"%0d %0h",aa,Bank2[bb]);
else
$fdisplay(sdram_data,"%0d %0h",aa,Bank3[bb]);
end
$fclose("sdram_data.txt");
sdram_mem=$fopen("sdram_mem.txt");
for(cc=0;cc<4*(mem_sizes+1);cc=cc+1)
begin
ee=cc[18:0];
if(cc<=mem_sizes)
$fdisplay(sdram_mem,"%0h",Bank0[ee]);
else if(cc<=2*mem_sizes+1)
$fdisplay(sdram_mem,"%0h",Bank1[ee]);
else if(cc<=3*mem_sizes+2)
$fdisplay(sdram_mem,"%0h",Bank2[ee]);
else
$fdisplay(sdram_mem,"%0h",Bank3[ee]);
end
$fclose("sdram_mem.txt");
end
// // // Timing Parameters for -75 (PC133) and CAS Latency = 2
// // specify
// // specparam
// tAH = 0.8, // Addr, Ba Hold Time
// tAS = 1.5, // Addr, Ba Setup Time
// tCH = 2.5, // Clock High-Level Width
// tCL = 2.5, // Clock Low-Level Width
// // tCK = 10.0, // Clock Cycle Time 100mhz
// // tCK = 7.5, // Clock Cycle Time 133mhz
// tCK = 7, // Clock Cycle Time 143mhz
// tDH = 0.8, // Data-in Hold Time
// tDS = 1.5, // Data-in Setup Time
// tCKH = 0.8, // CKE Hold Time
// tCKS = 1.5, // CKE Setup Time
// tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time
// tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time
// // tAH = 1, // Addr, Ba Hold Time
// // tAS = 1.5, // Addr, Ba Setup Time
// // tCH = 1, // Clock High-Level Width
// // tCL = 3, // Clock Low-Level Width
// tCK = 10.0, // Clock Cycle Time 100mhz
// tCK = 7.5, // Clock Cycle Time 133mhz
// // tCK = 7, // Clock Cycle Time 143mhz
// // tDH = 1, // Data-in Hold Time
// // tDS = 2, // Data-in Setup Time
// // tCKH = 1, // CKE Hold Time
// // tCKS = 2, // CKE Setup Time
// // tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time
// // tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time
// // $width (posedge Clk, tCH);
// // $width (negedge Clk, tCL);
// // $period (negedge Clk, tCK);
// // $period (posedge Clk, tCK);
// // $setuphold(posedge Clk, Cke, tCKS, tCKH);
// // $setuphold(posedge Clk, Cs_n, tCMS, tCMH);
// // $setuphold(posedge Clk, Cas_n, tCMS, tCMH);
// // $setuphold(posedge Clk, Ras_n, tCMS, tCMH);
// // $setuphold(posedge Clk, We_n, tCMS, tCMH);
// // $setuphold(posedge Clk, Addr, tAS, tAH);
// // $setuphold(posedge Clk, Ba, tAS, tAH);
// // $setuphold(posedge Clk, Dqm, tCMS, tCMH);
// // $setuphold(posedge Dq_chk, Dq, tDS, tDH);
// // endspecify
endmodule测试代码如下：
`timescale 1ns/1ns
module SDRAM_control_tb ();
reg rst_n;
reg clk;
parameter clk_period = 10;
localparam TWAIT_200us = 15'd20000;
localparam TRP = 2'd3;
localparam TRC = 4'd10;
localparam TRSC = 2'd3;
localparam TRCD = 2'd2;
localparam TREAD_10 = 4'd10;
localparam TWRITE_7 = 3'd7;
localparam AUTO_REF_TIME = 11'd1562;
localparam NOP = 3'd0;
localparam PRECHARGE = 3'd1;
localparam REF = 3'd2;
localparam MODE = 3'd3;
localparam IDLE = 3'd4;
localparam ACTIVE = 3'd5;
localparam WRITE = 3'd6;
localparam READ = 3'd7;
localparam NOP_CMD = 4'b0111;
localparam PRECHARGE_CMD = 4'b0010;
localparam REF_CMD = 4'b0001;
localparam MODE_CMD = 4'b0000;
localparam ACTIVE_CMD = 4'b0011;
localparam WRITE_CMD = 4'b0100;
localparam READ_CMD = 4'b0101;
localparam ALL_BANK = 12'b01_0_00_000_0_000;
localparam MODE_CONFIG = 12'b00_0_00_011_0_011;
reg wr_en;
reg [15:0] wr_data;
reg rd_en;
reg [1:0] bank_addr;
reg [11:0] row_addr;
reg [8:0] col_addr;
wire [15:0] rd_data;
wire rd_data_vld;
wire wr_data_vld;
wire wdata_done;
wire rdata_done;
wire sdram_clk;
wire [3:0] sdram_commond;
wire sdram_cke;
wire [1:0] sdram_dqm;
wire [11:0] sdram_addr;
wire [1:0] sdram_bank;
wire [15:0] sdram_dq;
//reg sdram_dq_en;
//reg sdram_dq_r;
//assign sdram_dq = sdram_dq_en ? sdram_dq_r : 16'hzzzz;
SDRAM_control inst_SDRAM_control
(
.clk (clk),
.rst_n (rst_n),
.wr_en (wr_en),
.wr_data (wr_data),
.rd_en (rd_en),
.bank_addr (bank_addr),
.row_addr (row_addr),
.col_addr (col_addr),
.rd_data (rd_data),
.rd_data_vld (rd_data_vld),
.wr_data_vld (wr_data_vld),
.wdata_done (wdata_done),
.rdata_done (rdata_done),
.sdram_clk (sdram_clk),
.sdram_commond (sdram_commond),
.sdram_cke (sdram_cke),
.sdram_dqm (sdram_dqm),
.sdram_addr (sdram_addr),
.sdram_bank (sdram_bank),
.sdram_dq (sdram_dq)
);
sdram_model_plus #(
.addr_bits(12),
.data_bits(16),
.col_bits(9),
.mem_sizes(2*1024*1024)
) inst_sdram_model_plus (
.Dq (sdram_dq),
.Addr (sdram_addr),
.Ba (sdram_bank),
.Clk (sdram_clk),
.Cke (sdram_cke),
.Cs_n (sdram_commond[3]),
.Ras_n (sdram_commond[2]),
.Cas_n (sdram_commond[1]),
.We_n (sdram_commond[0]),
.Dqm (sdram_dqm),
.Debug (1'b1)
);
initial clk = 1;
always #(clk_period/2) clk = ~clk;
initial begin
#1;
rst_n = 0;
wr_en = 0;
wr_data = 16'd0;
rd_en = 0;
bank_addr = 2'b00;
row_addr = 12'd0;
col_addr = 9'd0;
//sdram_dq_en = 0;
#(clk_period*20);
rst_n = 1;
#(clk_period*20);
#(20100*clk_period);
wr_en = 1;
row_addr = 12'd100;
col_addr = 9'd8;
#clk_period;
wr_en = 0;
row_addr = 12'd0;
#(clk_period*50);
rd_en = 1;
row_addr = 12'd100;
col_addr = 9'd8;
#clk_period;
rd_en = 0;
#(clk_period*50);
//测试读写优先级，应该是读优先级高于写优先级
wr_en = 1;
rd_en = 1;
row_addr = 12'd200;
col_addr = 9'd16;
#clk_period;
wr_en = 0;
rd_en = 0;
#(clk_period*50);
$stop;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
wr_data <= 0;
end
else if (wr_data_vld) begin
wr_data <= wr_data + 2'd2;
end
end
endmodule
仿真结果：
首先仿真的是初始化：
可以看到其加载模式寄存器就是自己配置的模式。下边进行读和写操作测试。
可以看到其读写测试和预想结果一样。
五、总结
SDRAM控制器设计的时候还是比较复杂的，根据自己的需求选择什么样的模式，选择什么样的控制。将数据手册多看几遍，理清楚其中的关系和过程就会比较简单啦。
还有接下来工作就是对ov7670视频数据流能通过VGA接口显示在显示器上，VGA设计页写了，到时候总结的时候这些综合起来就可以啦。
